WP1: Application requirements
For each addressed application, identify and characterize the main composing modules in terms of timing constraints, processing workload, power requirements, necessary libraries, memory footprint (instruction and data). Tasks suitable for hardware implementation in reconfigurable logic (FPGA) will be identified.
WP2: Hardware architectures
Identify, characterize and select the reference architecture/platform to use for each application. Target architectures are heterogeneous computing platforms for the embedded market characterized by a power consumption less than 10W. Examples include COTS architectures ARM big.LITTLE coupled with Mali GPU, and Nvidia Tegra X1 including two quad-core ARM big.LITTLE and a Maxwell GPU, as well as FPGA for implementation of domain-specific hardware accelerators. Analysis of hardware platforms will include a detailed characterization of the performance/cost (with special interest to the addressed market volume), power consumption, throughput, timing and predictability.
WP3: Programming models
Based on application requirements and addressed platform, identify programming models of interest to efficiently parallelize the addressed applications for the execution on the many-core fabric. Special care will be taken to ensure that appropriate performance analysis techniques for the chosen programming models are available, such that requirement of high-criticality tasks can be satisfied. Lightweight runtimes will be developed for efficient deployment of the parallel programming constructs on the target platforms, minimizing the memory requirement and power consumption.
WP4: Real-Time Operating Systems
This work-package will be split into two branches, to allow for a flexible approach that may be dynamically and predictably tuned to achieve the required power saving, timing precision, performance and library support.
- The selection/implementation of a general purpose OS for the host processor(s) with a proper support for the libraries adopted by the selected applications, and a design that allows achieving the required timing predictability and power efficiency. An example can be Linux with sched_deadline scheduling policy on top of the BIG cores.
- The selection/implementation of a lightweight MRTOS to execute the most time-critical activities in a timely fashion and a smaller power consumption. An example can be ERIKA kernel on the little cores, or as a partition of the BIG cores (with or without hypervisor/virtualization).
WP5: Scheduling and schedulability analysis
This work-package will be devoted to the design of power-aware scheduling algorithms that take into account the main bottlenecks of the architecture, and optimize performance considering the time criticality and required performance of each considered application. State-of-the-art real-time scheduling algorithms will be implemented for the management of processing cores, shared resources, memory bandwidth and data transfers, for the joint optimization of system performance and energy efficiency, without violating the application timing requirements.
WP6: Dissemination and exploitation
Evaluate the possibility of starting up a company to exploit the project results/products.
Include major companies from the automotive/avionics domain in the IAB.
Each partner is responsible of a work-package, with UNIMORE coordinating the whole project.